The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Scan-based testing is a technique that is used to internally test elements of a circuit under test (CUT), such as an application specific integrated circuit (ASIC). The testing may be performed to monitor operation of state variable devices (i.e. flip-flops and/or latches) and to detect core faults within the CUT. Scan-based testing includes replacing state variable devices that make up sequential circuits with pseudo inputs and outputs. Values of the pseudo inputs and outputs can be set arbitrarily and monitored by connecting memory elements and/or sequential logic devices of the CUT in a serial shift register configuration.
Each serial shift register is referred to as a scan chain. Serial shift (i.e. scan) actions are employed to set flip-flops of the CUT to an arbitrary set of values. Scan test data is shifted into the CUT, and resultant output test data is captured, sampled and monitored. This process transforms a sequential circuit into a virtual combinational circuit where scan in and out activities are defined as macro operations to set and monitor the state variables of the CUT.
Serial scanning becomes infeasible with increased circuit complexity and thus an increased number of state variables. For this reason, parallel scanning is implemented. In parallel scanning an overall scan chain is separated into a number of independently operable serial scan chains to reduce overhead. For example, a 100,000-bit serial scan chain may be implemented as 10 independently operable scan chains of 10,000 bits each. This implementation reduces the total number of shift cycles necessary to load and unload the 100,000 bits by a factor of 10.
Referring now to FIG. 1, a functional block diagram of a CUT 10 is shown. The CUT 10 includes scan chains 12, which are in parallel and have associated combinational logic circuits 14. The combinational logic circuits 14 communicate with and are positioned between the scan chains 12. The CUT 10 also includes multiple Scan_In and Scan_Out tester pins 16, 18. A pair of Scan_In and Scan_Out pins is associated with each of the scan chains 12. Scan test data, which may be controlled, is provided to the Scan_In pins 16. Output of the scan chains 12 may be monitored via the Scan_Out pins 18.
Parallel scanning may be limited to the number of independently operable scan chains that can be implemented on an integrated circuit (IC), but parallel scanning may also reduce the number of shift cycles of a scan-based test. Each independent scan chain may require a pair of Scan_In/Scan_Out pins that are directly accessible using primary I/O pins of the IC. The number of I/O pins available for scan testing purposes may be limited.
As integrated circuit devices grow in size, corresponding scan chains also grow in size. With an increase in scan chain size comes an increase in the number of shifts required to load and unload data. Also, the larger the scan chains, the more data that is required from and used by a test system, which may increase memory requirements to perform a test.
In addition, during scan testing automatic test pattern generation (ATPG) vectors are generated. For each ATPG vector, an input vector, an expected output vector, and a mask vector may be needed to indicate whether a test output bit value is reliable. Thus, a substantial amount of high-speed memory may be required to store test patterns and expected results. The total volume of test related data and the need for increased physical bandwidth (i.e. number of externally controllable parallel scan chains) are dominant factors in determining overall test cost for complex ICs.
As a result, data decompression and compression techniques are used to reduce the number of needed Scan_In/Scan_Out pins. A decompressor and a compressor may be provided on a CUT. As an example, scan test data may be provided to Scan_In pins, decompressed, and then provided to scan chains. Compressors may compress output signals of the scan chains and provided the output signals to Scan_Out pins. Put another way, a seed value may be scanned into a decompressor. The decompressor may then produce actual test values, which are fed into the scan chains. More scan chains are thus used with larger amounts of scan test data, which tends to shorten scan chain length. Reduced scan chain length may reduce test system memory requirements and test time.
Compression algorithms can be adversely affected by a high X-density. During scan testing, unknown data can occur. Unknown data is represented as an X. Unknown data is generated external to scan chains and can cause monitored data and faults to be masked. The term “mask” refers to the inability to monitor and reliably use certain discarded or hidden data.
Data may be unreliable when proper values of certain pin(s) are unknown, which can result from the reception of one or more Xs. Xs may be generated during a scan test from uncontrollable devices that have unknown outputs. Unknown outputs may be associated with, for example, random access memory (RAM)s, phase lock loops (PLL)s, delay lock loops (DLL)s, analog devices, embedded blocks, and/or other devices. A low level compression ratio of the associated compressor may provide variable test data results when a CUT experiences a high number of Xs during scan testing.
X-density of a CUT is based on the number of X's that occur during a load and unload of data. More particularly, X-density may equal the number of X's divided by the number of shifts that occur during a load and unload process. As an example, a CUT may experience 100 Xs and 1000 shifts for a single capture event. Thus, the CUT has an X-density of 0.1 Xs per shift. When the compression ratio is increased by ten (10) such that there are 100 shifts, the X-density is 1.0 Xs per shift. An X-density of 1.0 Xs per shift may render the compression output data useless.